Planar bipolar junction transistors (BJTs) are often used to fabricate integrated circuits. A planar BJT has an emitter electrode, a base electrode, and a collector electrode which are formed usually by diffusion or ion implantation technology and are not self-aligned. Planar BJTs, although used and useful in many integrated circuit applications, consume a large amount of substrate area per transistor and have high parasitic resistance and high parasitic capacitance. In addition, with integrated circuit geometries decreasing into sub-micron ranges, planar diffused BJTs have various disadvantages. Due to smaller geometries and heat cycles, well documented problems such as increased leakage currents, device isolation breakdown, deep diffusion junction depths, and unwanted dopant outdiffusion are major problems. In addition, a high series resistance may result in diffused BJTs and degrade both amplification and switching speed performance. Diffused BJTs are also difficult to scale, and diffusion wells are difficult to position and process consistently with respect to one another. The scaling, positioning, and processing problems result in devices that vary greatly in performance across a wafer. Furthermore, the diffused BJT typically has a current carrying capability that is not as high as desired.
In order to increase amplification and improve upon the scaling problem, BJTs are formed with an emitter electrode which is doped via an overlying polysilicon layer. Doping via an overlying polysilicon layer allows diffusion junctions to be relatively shallow. Although this single-polysilicon BJT process results in improved performance over the diffused BJT, the single-polysilicon BJT has several of the diffused BJT disadvantages. Some examples of known disadvantages include deep diffusions for the base and collector and a high series resistance.
To improve upon the single-polysilicon BJT, a double-polysilicon BJT is used. The double-polysilicon BJT uses a first layer of polysilicon for forming a base electrode and a second layer of polysilicon for forming an emitter electrode. Performance improves for the double-polysilicon BJT when compared to the single-polysilicon BJT. Due to a presence of exposed silicon regions, etch processing of the double-polysilicon BJT result in substrate trenching which leads to etch damage. This etch damage may result in increased leakage current and may increase series resistance. Furthermore, a physically large base region results which creates larger capacitance and therefore slows the operation of the double-polysilicon BJT.
A sidewall base contact structure (SICOS) BJT is used to improve performance. A very complicated process is required to form a conventional SICOS contact. A base is formed as a mesa by silicon etching, and the silicon etching may introduce silicon damage into the base region. A SICOS contact is formed by a complex photoresist etch-back scheme. The SICOS structure may be used to form both NPN or PNP bipolar transistors. In some cases, undesirable parasitics of NPN and PNP bipolar transistors are increased.